Static Random Access Memory (SRAM) is chosen as a reliable, proven technology for high-performance stand-alone memory devices or embedded memory devices. The distinct advantages of an SRAM include fast access speed, low power consumption, high noise margin, and process compatibility with a conventional CMOS fabrication process, among others. However, the size of the SRAM cell is limited by problems encountered in processing. This prevents the use of SRAM in devices that require very small SRAM cells. Further, processing requirements of conventional SRAM cells hinder the use of fin field effect transistors (FinFETs) in the SRAM. Thus, there is a need for a layout of an SRAM cell that obviates processing problems for small cell sizes and allows for the application of FinFETs in SRAM.
A conventional 6T SRAM layout may be used in 90 nm, 65 nm, 45 nm, and 32 nm technology, but problems occur that can prevent using the layout for smaller technology. For instance, as the cell size becomes smaller, the individual components, such as the active areas of the transistors, the intra-cell connections, and contacts, would naturally need to become smaller. Unfortunately, current lithography and etching techniques limit the size of individual components. Hence, once the individual components decrease to the smallest possible size, if the cell size continues to decrease, the components will cause a greater density within the cell and may overlay other components. Any overlay would lead to a short circuit between different components causing device failure.
Generally, a 6T SRAM cell comprises two pass-gate transistors, two pull-down transistors, and two pull-up transistors. Each pass-gate transistor typically shares a source/drain region with one of the pull-down transistors. Due to the layout and the desired electrical characteristics of the pass-gate transistor and the pull-down transistor, the active area is frequently non-rectangular such that an active zag is created between the active areas of the pass-gate transistor and the pull-down transistor where the active area changes direction or widths. These active zags generally create problems with current mismatch between the pull-down and pull-up transistors and leakage current between the pass-gate and pull-down transistors. The problems generally arise because of weaknesses in processing sharp corners, such as those of the active zag. Also, a strong electric field around the corner may cause leakage problems.
In the conventional layout, the active areas of the pass-gate and pull-down transistors usually adjoin such that the lengths of the active areas of the transistors largely define a dimension of the cell layout. Further, a single contact is usually formed to the active areas of those transistors between each transistor's gate. As a result, if the contact cannot be etched any smaller, the contact may also be a limiting factor; otherwise, overlay of the contact with the gate electrode spacers may result and adversely affect performance. Thus, any limitation on the size of the contact or spacers can further define the dimension of the cell layout. The length of this dimension can result in long bitlines that can increase line capacitance and can slow the performance of the SRAM cell.
The conventional layout also usually includes a butted contact wherein the butted contact electrically couples a metal on a first metallization layer to a gate of the pull-down transistor and the pull-up transistor. These butted contacts generally require multiple etching steps because the components that are to be contacted are at different depths. The multiple etching steps may generally create more costs in processing and may cause more processing control problems.
Furthermore, the conventional layout also is not generally compatible with the process for building FinFETs. Generally FinFETs and tri-gate transistors need to be the same width in SRAM cells, but by making the transistors the same width in the conventional layout, SRAM issues, such as instability of the SRAM due to a beta-ratio that is too low, may arise.
Accordingly, there is a need for a SRAM layout that overcomes these deficiencies of the prior art. Embodiments of the invention seek to solve or obviate the limitations and problems of conventional SRAM layouts, as generally discussed above, and gain further advantages discussed herein.